Input/output controller |
A bus is capable of being parallel or a serial bus and today all computers utilize two types of buses, an internal or local bus and an external bus. An internal bus enables a communication between internal components such as a computer video card and memory and an external bus is capable of communicating with external components such as a SCSI scanner.
A computer or devices bus speed or throughput is always measured in bits per second or megabytes per second.
All buses consist of two parts -- an address bus and a data bus. The data bus transfers actual data whereas the address bus transfers information about where the data should go.The size of a bus, known as its width, is important because it determines how much data can be transmitted at one time. For example, a 16-bit bus can transmit 16 bits of data, whereas a 32-bit bus can transmit 32 bits of data.
Every bus has a clock speed measured in MHz. A fast bus allows data to be transferred faster, which makes applications run faster. On PCs, the old ISA bus is being replaced by faster buses such as PCI.
Nearly all PCs made today include a local bus for data that requires especially fast transfer speeds, such as video data. The local bus is a high-speed pathway that connects directly to the processor.
Several different types of buses are used on Apple Macintosh computers. Older macs use a bus called NuBus, but newer ones use PCI.
In networking, a bus is a central cable that connects all devices on a local-area network (LAN). It is also called the backbone.
The Micro Channel architecture consists of an address bus, a data bus, an arbitration bus, a set of interrupt signals, and support signals. It uses synchronous and asynchronous procedures for data transfer between memory, I/O devices, and a controlling master. The controlling master can be a DMA controller, the system master (system processor), or a bus master. The features of the Micro Channel architecture are:
All Micro Channel participants are either masters or slaves. There are three types of masters and three types of slaves.
An adapter can incorporate either a master function, a slave function, or a combination of both. For example, an adapter might be designed to operate primarily as a DMA slave. However, it would also respond to certain I/O read and I/O write operations from the system master, making it an I/O slave. If the adapter contains RAM or ROM that is in the memory address space, it would be a memory slave when that memory was accessed.
The Micro Channel architecture consists of:
The highest value of the arbitration bus (hex F) has the lowest priority, and the lowest value (hex 0) has the highest priority. To participate in the arbitration procedure, an arbitrating participant must present its arbitration level immediately after the rising edge of ARB/-GNT . All arbitrating participants monitor the arbitration bus, and those with lower priority arbitration levels withdraw them by not driving less-significant arbitration bits.
The arbitration level of the highest-priority requester is valid on the arbitration bus after a settling time.
After the channel is granted to the highest-priority requester, that requester continues to drive its arbitration level on the bus.
Note: The system master can perform data transfers during arbitration ( ARB/-GNT in the ARB state).
The address bus and the associated signals are used by the controlling master to assert the memory address or the I/O address ( M/-IO ), to enable a slave to latch the address and status signals ( -S0, -S1 ), and to indicate that the memory address is greater than 16MB.
Note: A0 - A31 are used to transfer data during a 64-bit streaming data cycle.
During both read and write operations, a master generates a parity bit for each valid address byte, and the receiving slave optionally performs the parity checking to ensure the integrity of the address.
Note: APAR0 - APAR3 represent data parity during 64-bit streaming data cycle when -DPAREN is active.
APAR(0) represents the odd parity of D(32-39) . APAR(1) represents the odd parity of D(40-47) . APAR(2) represents the odd parity of D(48-55) . APAR(3) represents the odd parity of D(56-63) .
Note: Memory that contains diagnostic code must not drive -CD SFDBK during the diagnostic operation.
During a read cycle, a slave ensures that data is valid within the time specified after releasing the signal to a ready state. The slave also holds the data long enough for the controlling master to sample the data. A slave can also use this signal during a write cycle if more time is needed to store the data. This signal is initially driven from a valid unlatched address decode and status active.
Note: APAR(0) - APAR(3) represent data parity during 64-bit streaming data cycles when -DPAREN is active.
During write operations, a master generates a parity bit for each data byte being transferred, and the receiving slave optionally performs the parity checking to ensure the integrity of the data. During read operations, a slave generates a parity bit for each valid data byte, and the receiving master optionally performs the parity checking to ensure the integrity of the data.
DPAR(2) represents the odd parity of D(16-23) . DPAR(3) represents the odd parity of D(24-31) .
During write operations, a master generates a parity bit for each data byte being transferred, and the receiving slave optionally performs the parity checking to ensure the integrity of the data. During read operations, a slave generates a parity bit for each valid data byte, and the receiving master optionally performs the parity checking to ensure the integrity of the data.
This signal allows the controlling master to monitor the information about the selected slave's data port size. The -CD DS 16 signal from each slave, not on an adapter card, is included in the AND to generate -DS 16 RTN .
-DS 16 -DS 32
RTN RTN Data Port Size
1 1 8-Bit Data Port
1 0 Not Valid
0 1 16-Bit Data Port
0 0 32-Bit Data Port
-SDR(0) -SDR(1) Decoded Streaming Rate
1 1 Basic Transfer Cycle
0 1 10 MHz maximum (100 ns minimum cycle)
0 0 20 MHz maximum (50 ns minimum cycle)
1 0 Reserved
Data is transferred to or from the data bus based on -CMD and a latched decode of the address, the status lines ( -S0 exclusive-OR -S1 ), and M/-IO .
Slaves must support a full decode of -S0 and -S1 . The following table shows the states of M/-IO , -S0 , and -S1 in decoding I/O and memory read and write commands.
M/-IO -S0 -S1 Function
0 0 0 (see note below)
0 0 1 I/O Write Command
0 1 0 I/O Read Command
0 1 1 Inactive
1 0 0 (see note below)
1 0 1 Memory Write Command
1 1 0 Memory Read Command
1 1 1 Inactive
Note: These decodes are used in the 20 MHz streaming data transfer. Some systems execute system specific basic transfer procedures with both status signals active.
An I/O write command instructs an I/O slave to receive the data from the data bus. An I/O read command instructs an I/O slave to drive its data onto the data bus.
A memory write command instructs a memory slave to receive the data from the data bus. A memory read command instructs a memory slave to drive its data onto the data bus.
MEMORY BUS
The memory bus is used to transfer information between the cpu and main memorythe RAM in your system. This bus is usually connected to the motherboard chipset North Bridge or Memory Controller hub chip. Depending on the type of memory your chipset (and therefore motherboard) is designed to handle, the North Bridge runs the memory bus at various speeds. The best solution is if the memory bus runs at the same speed as the processor bus. Some computers also have a back side bus which connects the CPU to a memory cache. This bus and the cache memory connected to it are faster than accessing the system RAM via the front side bus. The maximum theoretical bandwidth of the front side bus is determined by the product of its width, its clock frequency and the number of data transfers it performs per clock tick. For example, a 32-bit (4-byte) wide FSB with a frequency of 100 MHz that performs 4 transfers/tick has a maximum bandwidth of 1600 MB/second. The number of transfers per tick is dependent on the technology used, with (for example) GTL+ offering 2 transfers/tick, EV6 4 transfers/tick, and AGTL+ 8 transfers/tick.
Systems that use PC133 SDRAM have a memory bandwidth of 1066MBps, which is the same as the 133MHz CPU bus. In another example, Athlon systems running a 266MHz processor bus also run PC2100 DDR-SDRAM, which has a bandwidth of 2133MBpsexactly the same as the processor bus in those systems. Systems running a pentium 4 with its 400MHz processor bus also use dual-channel RDRAM memory, which runs 1600MBps for each channel, or a combined bandwidth (both memory channels run simultaneously) of 3200MBps, which is exactly the same as the Pentium 4 CPU bus. Pentium 4 systems with the 533MHz bus run dual-channel DDR PC2100 or PC2700 modules, which match or exceed the throughput of the 4266MBps processor bus.
Running memory at the same speed as the processor bus negates the need for having cache memory on the motherboard. That is why when the L2 cache moved into the processor, nobody added an L3 cache to the motherboard. Some very high-end processors, such as the Itanium and Itanium 2 and the Intel Pentium 4 Extreme Edition, have integrated 2MB,4MB of full-core speed L3 cache into the CPU. However, the most recent high-performance chips, such as the new Pentium Extreme Edition, use only L1 and L2 cache. Thus, it appears that L2 cache will continue to be the most common type of secondary cache for the foreseeable future.
