MCA

Micro Channel Architecture

MCA was introduced by IBM in 1987. MCA, or the Micro Channel bus, was a competition for ISA bus. The MCA bus offered several additional features over the ISA such as a 32-bit bus (although there was also a 16-bit bus), automatically configure cards (similar to what Plug and Play is today), and bus mastering for greater efficiency.
(MCA) IBM's proprietary 32-bit bus, used in high-end PS/2 personal computers. Micro Channel is designed for multiprocessing. It eliminates potential conflicts that arise when installing new peripheral devices. MCA is *not* compatible with either EISA or XT bus architecture so older cards cannot be used with it.
As with the ROM BIOS in the first IBM PCs, figuring out the Micro Channel's secrets has been an arduous task of reverse engineering ever since the PS/2 line was announced. Consequently, the MCA has never become as wide spread as the competing EISA standard.

Micro Channel Architecture

The Micro Channel architecture consists of an address bus, a data bus, an arbitration bus, a set of interrupt signals, and support signals. It uses synchronous and asynchronous procedures for data transfer between memory, I/O devices, and a controlling master. The controlling master can be a DMA controller, the system master (system processor), or a bus master. The features of the Micro Channel architecture are:

• I/O data transfers of 8-, 16-, 24-, or 32-bits within a 64KB address space (16-bit address width).
• Memory data transfers of 8-, 16-, 24-, or 32-bits within a 16MB (24-bit address width) or 4GB (32-bit address width) address space.
• An arbitration procedure that enables up to 15 devices and the system master to bid for control of the channel.
• A basic transfer procedure that allows data transfers between masters and slaves.
• A direct memory access (DMA) procedure that supports multiple DMA channels. Additionally, this procedure allows a device to transfer data in bursts.
• An optional streaming data procedure that provides a faster data-transfer rate than the basic transfer procedure and allows 64-bit data transfers.
• Address- and data-parity enable and detect procedures.
• Interrupt sharing on all levels.
• A flexible system-configuration procedure that uses programmable registers.
• An adapter interface to the channel using:
  • A 16-bit connector with a 24-bit address bus and a 16-bit data bus
  • A 32-bit connector with a 32-bit address bus and a 32-bit data bus
  • An optional matched-memory extension
  • An optional video extension.
• Support for audio signal transfer (audio voltage-sum node).
• Support for both synchronous and asynchronous data transfer.
• An exception condition reporting procedure.
• Improved electromagnetic characteristics.

Micro Channel Participants

All Micro Channel participants are either masters or slaves. There are three types of masters and three types of slaves.

An adapter can incorporate either a master function, a slave function, or a combination of both. For example, an adapter might be designed to operate primarily as a DMA slave. However, it would also respond to certain I/O read and I/O write operations from the system master, making it an I/O slave. If the adapter contains RAM or ROM that is in the memory address space, it would be a memory slave when that memory was accessed.

Masters

A master is a participant that drives the address bus and data transfer control signals that cause data transfer to or from a slave. The channel supports up to 16 masters. The central arbitration control point and the Micro Channel arbitration procedure control ownership of the channel. The central arbitration control point grants ownership at the end of the arbitration procedure to highest-priority requester. The three types of masters are:

• System master A system master controls and manages the system configuration. It arbitrates for use of the channel. A system master can also be a default master. The default master is the master that owns the channel when no other master requires the channel. The system master supports data transfers with an I/O slave or a memory slave.
• Bus master A bus master arbitrates for use of the channel. A bus master supports data transfers with an I/O slave or a memory slave.
• DMA controller A DMA controller does not initiate arbitration for the channel; a DMA slave initiates and completes the arbitration procedure. The DMA controller monitors the arbitration bus to detect the DMA slave's arbitration level. A DMA controller supports data transfers with DMA slaves and memory slaves.

Slaves

A slave is a participant that sends and receives data under the control of a master. The slave responds to signals that are driven by the master. A slave is selected by the controlling master using Micro Channel procedures. The channel supports 8-, 16- and 32-bit data bus size in a slave. The data port size (8-, 16-, or 32-bits) describes the maximum width of the data transfer. For example, a 32-bit slave can support 8-, 16- 24-, or 32-bit data transfers. During a data transfer cycle, an 8-bit data port on a 32-bit slave acts like an 8-bit slave. The three types of slaves are:

• I/O slave I/O slaves are selected by their address within the I/O address space.
• Memory slave Memory slaves are selected by their address within the memory address space.
• DMA slave A DMA slave is selected by arbitration or, optionally, by its address within the I/O address space. A DMA slave initiates a request for the channel and arbitrates for the channel with arbitrating masters and other DMA slaves. The DMA controller provides the DMA slave with the address and data transfer signals required for data transfers. During a DMA write operation, the DMA slave provides the data, and the memory slave stores it. During a DMA read operation, the memory slave provides the data, and the DMA slave stores it.

Addressing Model

The Micro Channel addressing model consists of a memory address space and an I/O address space. During an I/O cycle, the 64KB I/O address space is addressed by the low-order 16 bits of the address bus. During a memory cycle, the memory address space is addressed by the address bus. The signals used for an address of up to 4GB are MADE 24 , M/-IO , and A0 through A31 of the address bus. An address of up to 16MB uses A0 through A23 plus MADE 24 and M/-IO .

Micro Channel Buses and Signals

The Micro Channel architecture consists of:

• An arbitration bus and associated signals
• An address bus and associated signals
• A data bus and associated signals
• Interrupt signals
• Other Micro Channel signals
• Optional extensions for:
  • Matched memory extension signals
  • Video extension signals.

Throughout this document, a minus sign (-) in front of a signal name indicates that the signal is active when it is at a low-voltage level. When no minus sign appears, the signal is active when it is at a high-voltage level. For example, -CMD specifies the signal is active low. Also, ARB/-GNT is in the ARB state when it is at a high level and is in the -GNT state when it is at a low level.

Arbitration Bus and Associated Signals

The arbitration bus and associated signals allow arbitrating participants (the system master, bus masters, and DMA slaves) to request and gain ownership of the channel. The resolution of multiple arbitration requests results in granting ownership of the channel to the highest-priority requester.

ARB0 - ARB3:

Arbitration Bus: These signals make up the arbitration bus. They are driven by the system master, bus masters, and DMA slaves to present their arbitration level when requesting ownership of the channel. ARB0 (least significant) through ARB3 (most-significant) support up to 16 arbitration levels.

The highest value of the arbitration bus (hex F) has the lowest priority, and the lowest value (hex 0) has the highest priority. To participate in the arbitration procedure, an arbitrating participant must present its arbitration level immediately after the rising edge of ARB/-GNT . All arbitrating participants monitor the arbitration bus, and those with lower priority arbitration levels withdraw them by not driving less-significant arbitration bits.

The arbitration level of the highest-priority requester is valid on the arbitration bus after a settling time.

After the channel is granted to the highest-priority requester, that requester continues to drive its arbitration level on the bus.

ARB/-GNT:

Arbitrate/-Grant: Only the central arbitration control point drives this signal. The negative-to-positive transition of ARB/-GNT initiates an arbitration cycle. When in the ARB state, this signal indicates an arbitration cycle is in progress. When in the -GNT state, this signal indicates the acknowledgment from the central arbitration control point to the arbitrating participants and the DMA controller that channel ownership has been granted. This signal is driven to the ARB state by the central arbitration control point following the end of transfer (EOT).

Note: The system master can perform data transfers during arbitration ( ARB/-GNT in the ARB state).

-BURST:

-Burst: This signal is optionally driven by the winning arbitrating participant or the DMA controller after ARB/-GNT is driven to the -GNT state. This signal indicates to the central arbitration control point that the controlling master will use the channel for one or more consecutive data transfer cycles. This type of data transfer is called burst transfer .

-PREEMPT:

-Preempt: This signal is used by arbitrating participants to request use of the channel through arbitration. Any arbitrating participant that requires ownership of the channel drives -PREEMPT active, causing an arbitration cycle to occur. When a participant is granted control of the channel, it stops driving -PREEMPT . All arbitrating participants that have not been granted ownership keep their requests pending by continuing to drive -PREEMPT active. All masters and DMA slaves that use burst transfer must receive -PREEMPT .

Address Bus and Associated Signals

The address bus and the associated signals are used by the controlling master to assert the memory address or the I/O address ( M/-IO ), to enable a slave to latch the address and status signals ( -S0, -S1 ), and to indicate that the memory address is greater than 16MB.

A0 - A23:

Address Bits 0 through 23: These lines, along with A24 through A31 , make up the address bus. These lines are driven by the controlling master to address memory, I/O slaves, and, optionally, DMA slaves. A0 is the least-significant bit and A23 is the most-significant bit. These 24 address lines allow access of up to 16MB of memory. Only the lower 16 address lines ( A0 through A15 ) are for I/O operations, and all 16 lines must be decoded by the I/O slave. Valid addresses, generated by the controlling master, are unlatched on the channel and, if required, must be latched by the slaves using either the leading or trailing edge of -ADL or the leading edge of -CMD .

A24 - A31:

Address Bits 24 through 31: These lines, along with A0 through A23 are driven by the controlling master to address memory attached to the channel. A0 is the least-significant bit and A31 is the most-significant bit. These additional address lines allow access of up to 4GB of memory. Valid addresses, generated by the controlling master, are unlatched on the channel and, if required, must be latched by the slaves using either the leading or trailing edge of -ADL or the leading edge of -CMD .

Note: A0 - A31 are used to transfer data during a 64-bit streaming data cycle.

-ADL:

-Address Decode Latch: This signal, driven by the controlling master, is provided as a convenient way for the slave to latch valid address decodes and status bits.

-APAREN:

-Address Parity Enable: This optional signal is driven active by the controlling master when the master places an address on the bus. This signal indicates to a slave that address parity is supported.

APAR0 - APAR3:

Address Parity Bits 0 through 3: These optional signals are driven by the controlling master when an address is placed on the address bus. These signals represent the odd parity of the address bits on the address bus during both read and write operations. (Odd parity is the condition where the total number of 1s in a byte of data, including the parity bit, is odd.) APAR(0) represents the odd parity of A(0-7) . APAR(1) represents the odd parity of A(8-15) . APAR(2) represents the odd parity of A(16-23) . APAR(3) represents the odd parity of A(24-31) .

During both read and write operations, a master generates a parity bit for each valid address byte, and the receiving slave optionally performs the parity checking to ensure the integrity of the address.

Note: APAR0 - APAR3 represent data parity during 64-bit streaming data cycle when -DPAREN is active.

APAR(0) represents the odd parity of D(32-39) . APAR(1) represents the odd parity of D(40-47) . APAR(2) represents the odd parity of D(48-55) . APAR(3) represents the odd parity of D(56-63) .

-CD SFDBK (n):

-Card Selected Feedback: This signal is driven active by the selected slave as a positive acknowledgement of the slave's selection. The (n) indicates this signal is unique to each channel connector (one independent signal per connector). This signal is unlatched. The slave does not drive -CD SFDBK during the configuration procedure ( -CD SETUP active). Any slave, not on an adapter card, provides a signal equivalent to the -CD SFDBK signal.

Note: Memory that contains diagnostic code must not drive -CD SFDBK during the diagnostic operation.

MADE 24:

Memory Address Enable 24: This signal is driven by the controlling master and decoded by all memory slaves, regardless of the size of their address-space. When this signal is active, A24 - A31 are undefined.

• A master driving only A0 - A23 drives MADE 24 active.
• A master driving A0 - A31 drives MADE 24 :
  • Active when all bits in A24 - A31 are 0
  • Inactive when any bit in A24 - A31 is 1.

M/-IO:

Memory/-Input Output: This signal is driven by the controlling master and decoded by all slaves. This signal selects a memory cycle or an I/O cycle. When this signal is in the M state, a memory cycle is selected. When this signal is in the -IO state, an I/O cycle is selected.

-SFDBKRTN:

Selected Feedback Return: This optional signal is generated by the system logic from the AND of the -CD SFDBK( n ) signals being driven by slaves. This signal is a positive acknowledgement to the master from the slave that the slave is at the address specified by the master. Masters that support address parity must receive this signal. The -CD SFDBK signal from each slave, not on an adapter card, is included in the AND to generate -SFDBKRTN .

Data Bus and Associated Signals

The data bus is used to transfer either 8, 16, 24, or 32 bits of data. The associated signals indicate the amount of data transferred by the master in a single transfer cycle, the size of the slave's data port, and the type (read or write) of the data transfer.

D0 - D15:

Data Bits 0 through 15: These lines, along with D16 - D31 , make up the data bus. The data bus is driven by any master or slave that is transferring data. These lines ( D0 - D15 ) provide data bits 0 through 15. D0 is the least-significant bit; D15 is the most-significant bit. The 16-bit transfers from the controlling master to an 8-bit slave are converted by the controlling master to two 8-bit transfers, and are transmitted on lines D0 through D7 . An 8-bit slave must use D0 through D7 to communicate with the controlling master.

D16 - D31:

Data Bits 16 through 31: These lines, along with D0 - D15 , make up the data bus. The data bus is driven by any master or slave that is transferring data. These lines ( D16 - D31 ) provide data bits 16 through 31. D0 is the least-significant bit; D31 is the most-significant bit. The 32-bit transfers from the controlling master to an 8-bit slave are converted to four 8-bit transfers by the controlling master, and are transmitted on lines D0 through D7 . The 32-bit transfers from the controlling master to a 16-bit slave are converted to two 16-bit transfers by the controlling master, and are transmitted on lines D0 through D15 .

-BE0 - -BE3:

-Byte Enable 0 through 3: These signals are used during data transfers with 32-bit slaves to indicate which data bytes are valid on the data bus. Data transfers of 8, 16, 24, or 32 contiguous bits are controlled by -BE0 through -BE3 during transfers involving 32-bit slaves only. These signals are driven by the controlling master when TR 32 is inactive, and by the central translator logic (for those operations involving a 16-bit master with a 32-bit slave) when TR 32 is active. These signals are not latched on the bus and, if required, are latched by 32-bit slaves.

-CD DS 16 (n):

-Card Data Size 16: This signal is driven by 16-bit and 32-bit slaves to indicate a 16-bit or 32-bit data port at the location addressed. The (n) indicates this signal is unique to each channel connector (one independent signal per connector). This signal is derived from an unlatched address decode. -CD DS 16 is not driven by 8-bit slaves and is inactive for an 8-bit data port. Any slave, not on an adapter card, provides a signal equivalent to the -CD DS 16 signal.

-CD DS 32 (n):

-Card Data Size 32: This signal, along with -CD DS 16 , is driven by 32-bit slaves to indicate a 32-bit data port at the location addressed. The (n) indicates this signal is unique to a channel connector position (one independent signal per connector). -CD DS 32 is derived from an unlatched address decode. -CD DS 32 is inactive for an 8- or 16-bit data port. Any slave, not on an adapter card, provides a signal equivalent to the -CD DS 32 signal.

CD CHRDY (n):

Channel Ready: This signal is normally active (ready) and is driven inactive (not ready) by a slave to allow additional time to complete a channel cycle. The (n) indicates this signal is unique to each channel connector (one independent signal per connector). Any slave, not on an adapter card, provides a signal equivalent to the -CD CHRDY signal.

During a read cycle, a slave ensures that data is valid within the time specified after releasing the signal to a ready state. The slave also holds the data long enough for the controlling master to sample the data. A slave can also use this signal during a write cycle if more time is needed to store the data. This signal is initially driven from a valid unlatched address decode and status active.

CHRDYRTN:

Channel Ready Return: This signal is the AND of CD CHRDY ( n ) . It is driven by the system logic. If all slaves drive CD CHRDY active, this signal is active. CHRDYRTN allows the controlling master to monitor the ready information. The -CD CHRDY signal from each slave, not on an adapter card, is included in the AND to generate -CHRDYRTN .

-CMD:

-Command: This signal is driven by the controlling master and is used to define when data on the data bus is valid. The trailing edge of this signal indicates the end of the bus cycle. During write cycles, the data is valid as long as -CMD is active. During read cycles, the data is valid after the leading edge, but before the trailing edge, of -CMD and is held on the bus until after -CMD goes inactive. Slaves can latch address and status information with the leading edge of -CMD .

-DPAREN:

-Data Parity Enable: This optional signal is driven active by the participant when data is placed on the data bus. This signal indicates that the data parity signals are valid.

Note: APAR(0) - APAR(3) represent data parity during 64-bit streaming data cycles when -DPAREN is active.

DPAR0 - DPAR1:

Data Parity Bits 0 and 1: These optional signals are driven by the participant when data is placed on the data bus. These signals represent the odd parity of the data bits on the data bus during both read and write operations. (Odd parity is the condition where the total number of 1s in a byte of data, including the parity bit, is odd.) DPAR(0) represents the odd parity of D(0-7) . DPAR(1) represents the odd parity of D(8-15) .

During write operations, a master generates a parity bit for each data byte being transferred, and the receiving slave optionally performs the parity checking to ensure the integrity of the data. During read operations, a slave generates a parity bit for each valid data byte, and the receiving master optionally performs the parity checking to ensure the integrity of the data.

DPAR2 - DPAR3:

Data Parity Bits 2 and 3: These optional signals are driven by the participant when data is placed on the data bus. These signals represent the odd parity of the data bits on the data bus during both read and write operations.

DPAR(2) represents the odd parity of D(16-23) . DPAR(3) represents the odd parity of D(24-31) .

During write operations, a master generates a parity bit for each data byte being transferred, and the receiving slave optionally performs the parity checking to ensure the integrity of the data. During read operations, a slave generates a parity bit for each valid data byte, and the receiving master optionally performs the parity checking to ensure the integrity of the data.

-DS 16 RTN:

-Data Size 16 Return: This signal is driven by the system logic. This signal is the AND of -CD DS 16 ( n ) from each channel connector. If any slave drives its -CD DS 16 active, this signal is active.

This signal allows the controlling master to monitor the information about the selected slave's data port size. The -CD DS 16 signal from each slave, not on an adapter card, is included in the AND to generate -DS 16 RTN .

-DS 32 RTN:

-Data Size 32 Return: This signal is driven by the system logic. This signal is the AND of -CD DS 32 ( n ) from each channel connector. If any slave drives its -CD DS 32 active, this signal is active. This signal allows the controlling master to monitor the information about the selected slave's data port size. The -CD DS 32 signal from each slave, not on an adapter card, is included in the AND to generate -DS 32 RTN .

     -DS 16      -DS 32
    RTN         RTN          Data Port Size
    1           1            8-Bit Data Port
    1           0            Not Valid
    0           1            16-Bit Data Port
    0           0            32-Bit Data Port

-MSDR:

-Multiplexed Streaming Data Request: This optional signal is driven by a slave to indicate to the controlling master that the slave is capable of 64-bit streaming data transfers.

-SBHE:

-System Byte High Enable: This signal is driven by the controlling master to indicate and enable transfers of data on D8 - D15 . It is used with A0 to distinguish between high-byte transfers ( D8 - D15 ) and low-byte transfers ( D0 - D7 ) and double-byte (16-bit) transfers to 16-bit data ports. All 16-bit slaves receive this signal.

-SD STROBE:

-Streaming Data Strobe: The controlling master and the slave use this signal to clock data on and off the data bus. This optional signal is driven by the controlling master. This signal also indicates to the slave that the controlling master supports streaming data.

-SDR(0):

-Streaming Data Request 0: This optional signal is driven by a slave to indicate to the controlling master that the slave is capable of streaming data, and also indicates the maximum clocking rate the slave supports.

-SDR(1):

-Streaming Data Request 1: This optional signal is driven by a slave to indicate to the controlling master that the slave is capable of streaming data, and also indicates the maximum clocking rate the slave supports.

     -SDR(0)     -SDR(1)      Decoded Streaming Rate
    1           1            Basic Transfer Cycle
    0           1            10 MHz maximum (100 ns minimum cycle)
    0           0            20 MHz maximum (50 ns minimum cycle)
    1           0            Reserved

-S0, -S1:

-Status 0, -Status 1: These status signals are driven by the controlling master to indicate the start of a data transfer cycle and also define the type of data transfer. When used with M/-IO , memory read or write cycles are distinguished from I/O read or write cycles. These signals are latched by the slave, as required, using the leading edge of -CMD , or the leading or trailing edge of -ADL.

Data is transferred to or from the data bus based on -CMD and a latched decode of the address, the status lines ( -S0 exclusive-OR -S1 ), and M/-IO .

Slaves must support a full decode of -S0 and -S1 . The following table shows the states of M/-IO , -S0 , and -S1 in decoding I/O and memory read and write commands.

     M/-IO       -S0          -S1         Function
    0           0            0           (see note below)
    0           0            1           I/O Write Command
    0           1            0           I/O Read Command
    0           1            1           Inactive
    1           0            0           (see note below)
    1           0            1           Memory Write Command
    1           1            0           Memory Read Command
    1           1            1           Inactive

Note: These decodes are used in the 20 MHz streaming data transfer. Some systems execute system specific basic transfer procedures with both status signals active.

An I/O write command instructs an I/O slave to receive the data from the data bus. An I/O read command instructs an I/O slave to drive its data onto the data bus.

A memory write command instructs a memory slave to receive the data from the data bus. A memory read command instructs a memory slave to drive its data onto the data bus.

-TC:

-Terminal Count: This signal is driven by the DMA controller and provides a pulse during a read or write command to the DMA slave to indicate that the terminal count of the current DMA channel has been reached. This indicates to the DMA slave that this is the last cycle to be performed. -TC is driven active on the channel during DMA operations only.

TR 32:

Translate 32: This signal is driven inactive by 32-bit controlling masters and received by the central translator logic. The signal indicates to the central translator logic that the controlling master is performing data steering. TR 32 can also be received by any 32-bit slave.

Interrupt Signals

-IRQ 3-7, -IRQ 9-12, and -IRQ 14-15:

-Interrupt Request: An interrupt request is generated when an I/O slave drives one of the ]interrupt requestä signals low. These signals make up the set of interrupt signals. The polarity of these signals makes it possible for multiple slaves to concurrently share the same interrupt level.